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Description: 用Verilog语言实现的FPGA UART独立收发模块
思路简单,代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond.
功能:串口收到数据后立即回传,此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
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Size: 3072 |
Author: 朱强光 |
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Description: 用verilog编写的uart代码,比较适合初学者练练手,包含初始化,收发等模块-Written code with verilog uart, more suitable for beginners practice your hand, including initialization, sending and receiving modules
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Size: 201728 |
Author: renyanpeng |
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Description: Verilog状态机实现的串口串口收发模块 -Verilog state machine for uart
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Size: 1205248 |
Author: fu |
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Description: 使用verilog语言实现的UART控制器,包含发送和接收部分,波特率可调。-Using the UART controller verilog language, including sending and receiving part, the baud rate is adjustable.
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Size: 114688 |
Author: 张秋光 |
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Description: URAT资料,用verilog HDL编写,具有完整的信号描述和功能-URAT data write complete signal description and function, with verilog HDL
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Size: 51200 |
Author: 牛玉祥 |
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Description: verilog写的串口程序,其功能完全最正确,带工程文件-verilog to write the serial program, its function is completely the right, with the project file
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Size: 433152 |
Author: 潘政 |
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Description: verilog实现UART,分模块实现,希望对大家有所帮助-verilog-- UART
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Size: 4096 |
Author: 马少文 |
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Description: verilog uart串口通讯程序设计 带个模块详细设计 及说明文档-Verilog the uart serial communication program design with the detailed design and documentation of a module
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Size: 4130816 |
Author: 邓烨 |
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Description: verilog uart 源码,编译器ISE9.1i版本,很有用的源码-verilog uart code
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Size: 100352 |
Author: xiabo |
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Description: FPGA上的verilog 的uart实现方法-FPGA on the verilog uart implementation
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Size: 2048 |
Author: 陆建强 |
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Description: 基于ISE 用verilog编写的uart串口通信源码-Based on the ISE written in verilog uart serial communication source code
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Size: 1024 |
Author: 祁伟 |
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Description: Verilog UART is written in this file
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Size: 4096 |
Author: teja |
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Description: 用Verilog实现UART,并且附有详细说明那个-The Verilog UART, and with the detailed description that
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Size: 144384 |
Author: 史欧文 |
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Description: verilog HDL 描写的uart程序
由PC端接收然后+1返回 等等
东南大学09级4系综合课程设计-verilog HDL description uart program
Received by the PC side and then+1 back。
SEU..
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Size: 588800 |
Author: yu |
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Description: UART(Universal Asynchronous Receiver Transmitter,通用异步收发器)是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路,分析UART的传输时序并利用Verilog HDL语言进行建模与仿真,最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receiver Transmitter) is a widely used asynchronous serial data communication protocol. Below first introduced UART hardware interface and level conversion circuit, the UART transmit timing analysis and use of Verilog HDL language modeling and simulation, and finally the development board connected to the PC via RS-232 communications conducted to test the correctness of UART transceiver.
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Size: 117760 |
Author: 李科 |
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Description: 用verilog编写的UART串口通信程序,经验证误码率为0,系统由ARM控制FPGA的串口进行通信;-Written in verilog UART serial communication procedures, proven error rate is 0, the system controlled by ARM FPGA serial communication
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Size: 3072 |
Author: lejing |
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Description: FPGA Verilog UART 通信源代码-FPGA Verilog THIS IS A UART SQC
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Size: 1024 |
Author: liweic |
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Description: 基于verilog的串口通信实验指导和源程序-Verilog based serial communication experiment guide and source code
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Size: 3122176 |
Author: 宋江 |
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Description: FPGA verilog UART串口通信,可通过RS232串口与串口助手通信。-FPGA verilog UART communication, it could connect with UART assistor with RS232 port.
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Size: 8192 |
Author: john |
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Description: Verilog 串口程序,可完成完整的数据接收与发送。代码注释清晰,程序易读。-Verilog UART
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Size: 1784832 |
Author: ouhongshi |
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